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ace24 lc 02 / 04/08/16 two - wire serial eeprom ver 1. 6 1 description the ace24 lc 02/04/08/16 p rovides low operation voltage of 2048/4096/8192/16384 bits of serial electrically erasable and progr ammable read - only memory (eeprom) organized as 256/512/1024/2048 words of 8 bits each. the device is optimized for use in many industrial and commercial applications where low - power and low - voltage operations are essential. features ? low operation voltage: vcc=1.7v to 3.6v ? 5v tolerant i/o ? internally organized: 2 5 6x 8 (2k), 512x8(4k), 1024x8(8k) or 204 8 x8(16k) ? two - wire serial interface ? schmitt trigger, filtered inputs for noise suppression ? bi - directional data transfer protocol ? 1mhz ( 3.6 v ,2.7v,2.5v ) and 400 khz (1.7v) compatibility ? write protect pin for hardware data protection ? 8 - byte page ( 2k ), 16 - byte page (4 k ,8 k ,16 k ) write mo des ? partial page writes are allowed ? self - timed write cycle (5 ms max) ? h igh - reliability - endurance: 1,000,000 write cycles - data retention: 100 years absolute maximum ratings operating temperature - 55 to +125 storage temperature - 65 to +150 voltage on any pin with respect to ground - 1.0v to +7.0v maximum operating voltage ace24 lc 02/04/08/16 6.25v dc output current 5.0 ma *n otice : stresses beyond those listed under absolute maximum ratings ma y cause permanent dam age to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification are not implied. exposure to absolute maxi mum rating conditions for extended periods may affect device reliability .
ace24lc02 / 04/08/16 two - wire serial eeprom ver 1. 6 2 packaging type pin configurations pin name function a0~a2 device address inputs sda serial data input / output scl serial clock input wp write protect v cc power supply gnd ground
ace24lc02 / 04/08/16 two - wire serial eeprom ver 1. 6 3 block diagram figure 1
ace24lc02 / 04/08/16 two - wire serial eeprom ver 1. 6 4 ordering information ace24 lc 02/04/08/16 xx + x h s erial c lock (scl) : the scl input is u sed to positive edge clock data into each eeprom device and negative edge clock data out of each device. s erial d ata (sda) : the sda pin is bi - directional for serial data transfer. this pin is open - drain driven and may be wire - ored with any number of other open - drain or open - collector devices. d evice /p age a ddresses (a2 , a1 , a 0 ) : the a2, a1 and a0 pins are device address inputs that are hard wired for the ace24 lc 02, as many as eight 2k devices may be addressed on a single bus system (device addressing is di scussed in detail under the device addressing section). the ace24 lc 04 uses the a2 and a1 inputs for hard wire addressing and a total of four 4k devices may be addressed on a single bus system. the a0 pin s are no co n n e c t s . the ace24 lc 08 only uses a2 input f or hardwire addressing and a total of two 8k devices may be addressed on a single bus system. the a0 and a1 pins are no connects. the ace24 lc 16 does not use the device address pins, which limits the number of devices on a single bus to one. the a0, a1 and a2 pins are no connects. w rite p rotect (wp): the ace24 lc 02/04/08/16 has a write protect pin that provides hardware data protection. the write protect pin allows normal read/write operations when connected to ground (gnd). when the write protect pin is con ceded to vcc the write protection feature is enabled. write protect description wp pin status part of the array protected ace24 lc 02 ace24 lc 04 ace24 lc 08 ace24 lc 16 wp= v cc full (2k) array full (4k) array full (8k) array f u l l ( 1 6 k) array wp= gnd norm al read / write operations pb - free u : tube t : tape and reel dp : dip - 8 fm : sop - 8 tm : tssop - 8 bn : sot - 23 - 5 dm : tdfn - 8 halogen - free
ace24lc02 / 04/08/16 two - wire serial eeprom ver 1. 6 5 memory organization ace 24 lc 02, 2k serial eeprom: internally organized with 32 pages of 8 bytes each, the 2k requires an 8 - bit data word address for random word addressing. ace 24 lc 04, 4k serial eeprom: internally organized w ith 32 pages of 16 bytes each, the 4k requires a 9 - bit data word address for random word addressing. ace24 lc 08 , 8k serial eeprom: internally organized with 64 pages of 16 bytes each, the 8k requires a 10 - bit data word address for random word addressing. a ce 24 lc 16, 16k serial eeprom: internally organized with 128 pages of 16 bytes each, the 16k requires an 11 - bit data word address for random word addressing. p in capacitance applicable over recommended operating range from: t a = 25 , f = 1.0 mhz, v cc = + 1.7 v. symbol test condition max units conditions c i/o 1 input / output capacitance (sda) 8 pf v i/o = 0v c in 1 input capacitance (a 0 , a 1 , a 2 , scl) 6 pf v in = 0v note : 1 . this parameter is characterized and is not 100% tested . dc c haracteristics applicable over recommended operating range from : t a = - 40 to +85 , v cc = + 1.7 v to + 3.6 v, (unless otherwise noted). symbol parameter test condition min typ max units v cc supply voltage 1.7 3.6 v i cc1 supply current v cc = 3.6 v, read at 100 k 0.4 1.0 ma i cc2 supply current v cc = 3.6 v, write at 1 00k 2 . 0 2.0 ma i sb1 standby current v cc = 1.7 v, v in = v cc / v ss 1.0 a i sb2 standby current v cc = 3.6 v, v in = v cc / v ss 3.0 a i li input leakage current v in = v cc /v ss 0.10 3.0 a i lo output leakage current v out = v cc / v ss 0.05 3.0 a v il 1 input low level - 0.6 v cc x0.3 v v ih 1 input high level v cc x0.7 5.5 v v ol 2 output low level v cc = 3.0 v, i ol = 2.1 ma 0.4 v v ol 1 output low level v cc = 1.8 v, i ol = 0.15 ma 0. 2 v note: 1. v il min and v ih max are reference only and are not tested.
ace24lc02 / 04/08/16 two - wire serial eeprom ver 1. 6 6 ac characteristics applicable over recommended operating range from : t a = - 40 to +85 , v cc = + 1.7 v to + 3.6 v, cl = 100 pf (unless otherwise noted). test conditions are listed in note 2. symbol parameter 1.7 - volt 2. 5 - volt 3.6 - volt units min max min max min max f scl clock frequency, scl 400 1000 1000 khz t low clock pulse width low 1 .3 0.4 0.4 s t high clock pulse width high 0.6 0.4 0.4 s t aa clock low to data out valid 0.05 0.9 0.05 0.55 0.05 0.55 s t buf 1 time the bus must be free before a new transmission can start 1. 2 0.5 0.5 s t hd.sta start hold time 0.6 0.25 0.2 5 s t su.sta start setup time 0.6 0.25 0.25 s t hd.dat data in hold time 0 0 0 s t su.dat data in setup time 100 100 100 ns t r inputs rise time 0.3 0.3 0.3 s t f inputs fall time 300 100 100 ns t su.sto stop setup time 0.6 0.25 0.25 s t dh data out hold time 50 50 50 ns t wr write cycle time 5 5 5 ms endurance 1 3.3 v, 25 , page mode 1,000,000 write cycles notes: 1. this parameter is characterized and not 100% tested. 2.ac measurement conditions: rl (connects to vcc): 1.3k input pulse voltages: 0.3 vcc to 0.7 vcc input rise and fall times: Q 5 0 ns input and output timing reference voltages: 0.5vcc device operation c lock and d ata t ransitions : the sda pin is nor mally pulled high with an external device. data on the sda pin may change only during scl low time periods (refer to figure 4 ). data changes during scl high periods will indicate a start or stop condition as defined below. s tart c ondition : a high - to - low transition of sda with scl high is a start condition which must precede any other command (refer to figure 5 ).
ace24lc02 / 04/08/16 two - wire serial eeprom ver 1. 6 7 s top c ondition : a low - to - high transition of sda with scl high is a stop condition. after a read sequence, the stop command will place the eeprom in a standby power mode (refer to figure 5 ). a c k n o w l e d g e : all addresses and data words are serially transmitted to and from the eeprom in 8 - bit words. the eeprom sends a zero during the ninth clock cycle to acknowledge that it has received each word. the happens during the ninth clock cycle. following receipt each word from the eeprom, the microcontroller should send a zero to eeprom and cont inue to output the next data word or send a stop condition to finish the read cycle. s tandby m ode : the ace 24 lc 02/04/08/16 features a low - power standby mode which is enabled: (a) upon power - up and (b) after the receipt of the stop bit and the completion o f any internal operations. device reset : after an interruption in protocol power loss or system reset, any two - wire part can be protocol reset by following these steps: 1. clock up to 9 cycles. 2. look for sda high in each cycle while scl is high and then. 3. cre ate a start condition. bus timing figure 2 scl: serial clock , sda: serial data i/o
ace24lc02 / 04/08/16 two - wire serial eeprom ver 1. 6 8 write cycle timing figure 3 scl: serial clock, sda: serial data i/o note: the write cycle time t wr is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle. figure 4 data validity figure 5 start and stop definition
ace24lc02 / 04/08/16 two - wire serial eeprom ver 1. 6 9 figure 6 output acknowledge device addressing the 2k, 4k, 8k and 16k eeprom devices all require an 8 - bit device address word following a start con dition to enable the chip for a read or write operation (refer to figure 7 ). the device address word consists of a mandatory one, zero sequence for the first four most significant bits as shown. this is common to all the eeprom devices. the next 3 bits are the a2, a1 and a0 device address bits for the 2k eeprom. these 3 bits must compare to their corresponding hard - wired input pins ( t h e a 2 , a 1 a n d a 0 d e v i c e a d d r e s s b i t s a r e 0 f o r t h e 2 k e e p r o m o f s t o - 2 3 - 5 p a c k a g e ) the 4k eeprom only uses the a2 and a1 device address i n g . t h e t h i r d b i t i s a m e m o r y p a g e a d d r e s s b i t . t h e a 2 , a 1 b i t m u s t c o m p a r e t o i t s c o r r e s p o n d i n g h a r d - w i r e d i n p u t p i n . t h e a 0 p i n i s n o c o n n e c t i n g . the 8k eeprom only uses the a2 device address bit with the next 2 bits being for memory page addressing. the a2 bit must compare to its corresponding hard - wired input pin. the a1 and a0 pins are no connect i n g . the 16k does not use any device address bits but instead the 3 bits are used for memory page addressing. these page addressing bits on the 4k, 8k and 16k device s should be considered the most significant bits of the data word address which follows. the a0, a1 and a2 pins are no connect. the eighth bit of the device address is the read/write operation select bit. a read operation is initiated if this bit is high a nd a write operation is initiated if this bit is low. upon a compare of the device address, the eeprom will output a zero. if a compare is not made, the chip will return to a standby state. write operations b yte w rite : a write operation requires an 8 - bit data word address following the device address word and acknowledgment. upon receipt of this address, the eeprom will again respond with a zero and then clock in the first 8 - bit data word. following receipt of the 8 - bit data word, the eeprom will output a zero and the addressing device, such as a microcontroller, must terminate the write sequence with a stop condition. at this time the eeprom enters an internally timed write cycle, t wr, to the nonvolatile memory. all inputs are disabled during this write c ycle and the eeprom will not respond until the write is complete (refer to figure 8 ).
ace24lc02 / 04/08/16 two - wire serial eeprom ver 1. 6 10 p age w rite : the 2k eeprom is capable of an 8 - byte page write, and the 4k, 8k and 16k devices are capable of 16 - byte page writes. a page write is initiated the same as a byte write, but the microcontroller does not send a stop condition after the first data word is clocked in. instead, after the eeprom acknowledges receipt of the first data word, the microcon troller can transmit up to seven (2k) or fifteen (4k, 8k, 16k) mo re data words. the eeprom will respond with a zero after each data word received. the microcontroller must terminate the page write sequence with a stop condi tion (refer to figure 9 ). the data word address lower three (2k) or four (4k, 8k, 16k) bits are in ternally incremented following the receipt of each data word. the higher data word address bits are not incremented, retaining the memory page row location. when the word address, internally generated, reaches the page boundary, the following byte is place d at the beginning of the same page. if more than eight (2k) or sixteen (4k, 8k, 16k) data words are transmitted to the eeprom, the data word address will roll over and previ ous data will be overwritten. a cknowledge p olling : once the internally timed write cycle has start ed and the eeprom inputs are dis abled, acknowledge polling can be initiated. this involves sending a start condition followed by the device address word. the read/write bit is representative of the operation desired. only if the intern al write cycle has completed will the eeprom respond with a zero allowing the read or write sequence to continue. read operations read operations are initiated the same way as write operations with the exception that the read/write select bit in the device address word is set to one. there are three read operations: current address read, random address read and sequential read. c urrent a ddress r ead : the internal data word address counter maintains the last address accessed dur ing the last read or write operation, incremen ted by one. this address stays valid between operations as long as the chip power is maintained. the address roll over during read is from the last byte of the last memory page to the first byte of the first page. the address roll over during write is from the last byte of the current page to the first byte of the same page. once the device address with the read/write select bit set to one is clocked in and acknowledged by the eeprom, the current address data word is serially clocked out. the microcontr oller does not respond with an input zero but does generate a following stop condition (refer to figure 10 ). r andom r ead : a random read requires a dummy byte write sequence to load in the data word address. once the device address word and data word add ress are clocked in and acknowledged by the eeprom, the microcontroller must generate another start condition. the microcontroller now initiates a current address read by sending a device address with the read/write select bit high. the eeprom acknowledges the device address and serially clocks out the data word. the microcontroller does not respond with a zero but does generate a following stop condition (refer to figure 11 ).
ace24lc02 / 04/08/16 two - wire serial eeprom ver 1. 6 11 s equential r ead : sequential reads are initiated by either a current address read or a random address read. after the microcontroller receives a data word, it responds with an acknowledge. as long as the eeprom receives an acknowledge, it will continue to increment the data word address and serially clock out sequential data words. whe n the memory address limit (2k,8k,16k) is reached, the data word address will roll over and the sequential read will continue. the sequential read operation is terminated when the microcontroller does not respond with a zero but does generate a following stop condition (refer to figure 12 ). figure 7 device address figure 8 byte write figure 9 page write
ace24lc02 / 04/08/16 two - wire serial eeprom ver 1. 6 12 figure 10 current address read figure 11 random read figure 12 sequential read
ace24lc02 / 04/08/16 two - wire serial eeprom ver 1. 6 13 packaging information dip - 8
ace24lc02 / 04/08/16 two - wire serial eeprom ver 1. 6 14 packaging information sop - 8
ace24lc02 / 04/08/16 two - wire serial eeprom ver 1. 6 15 packaging information tssop - 8
ace24lc02 / 04/08/16 two - wire serial eeprom ver 1. 6 16 packaging information s o t - 2 3 - 5
ace24lc02 / 04/08/16 two - wire serial eeprom ver 1. 6 17 packaging information tdfn - 8
ace24lc02 / 04/08/16 two - wire serial eeprom ver 1. 6 18 notes ace does not assume any responsibility for use as critical components in life support devices or systems without the express written approval of the president and general counsel of ace electro nics co., ltd. as sued herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and shoes failure to perform when properly used in accordance with instruction s for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. ace technology co., ltd. http://www.ace - ele.com/

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